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This is how a PLL synthesizer works

The PLL synthesizer makes it possible to equip receivers, transmitters and radios with a large number of crystal-stable channels without the need for a corresponding number of crystals. It uses both digital and analog technology and allows a non-crystal-controlled oscillator to be controlled in terms of its frequency in such a way that the desired frequencies are precisely adhered to. By the way, PLL means Phase Locked Loop.

The stability requirements of the channel respectively local oscillator are therefore not so high. However, it must be designed in such a way that its oscillation frequency can be influenced by means of a DC control voltage. For this purpose, the resonant circuit capacitance is usually formed in part by a capacitance diode. Such an oscillator is called a VCO. This abbreviation stands for Voltage Controlled Oscillator. Such an oscillator is always part of the PLL synthesizer. It belongs to its analog circuit part.

What is special about the PLL synthesizer is that the desired frequency can be changed using digital coding. The synthesizer must generate a control voltage from this code, which ensures that the VCO generates the frequency required for the set channel. If, for example, the values of the oscillating circuit elements change due to temperature changes, the control voltage must counteractedly correct it. We are hence dealing with a control loop. As a result, the PLL synthesizer must evaluate the currently generated frequency and compare it with a reference signal. VCO and reference signals are evaluated in their phase position. If the phase relationship deviates, this is a sign that the control voltage is trying to prevent an escape of the VCO frequency. Even before there is a significant change in frequency, the PLL corrects the phase relationship and thereby keeps the VCO frequency stable.

In the state where the frequency of the VCO is controlled by the PLL, one speaks of the PLL being locked. The unlocked state should be avoided during operation, because the radio system controlled by the VCO would work on more or less random frequencies in this case. A sign of this is a relatively slowly pulsating control voltage of the VCO, which can be easily evaluated with a simple circuit. This can be used, for example, to switch on a warning LED. In the case of commercially manufactured devices, the operation of the transmitter or radio system is completely blocked in this case. Provided that all components are working properly, this state never occurs if the VCO in the PLL synthesizer is correctly adjusted.

There are various circuits with which a control voltage can be generated from a phase difference. These initially deliver pulses that are converted into a DC voltage by means of an integrator respectively with the loop filter. The required comparison pulses for example can be generated with a ring mixer, a Gilbert cell or an exclusive-OR gate. There are various other arrangements that can be used as well having various advantages and disadvantages. In particular, those concern the catching area and the catching behavior. Depending on this, there are especially differences in the relative range related to the generated frequency in which the PLL is able to control the VCO. Other differences concern the duration of the control process and in the transient response. PLL synthesizers with a less than good phase comparator produce clearly disorder noises when switched on, especially in FM devices.

The reference signal is generated in the PLL synthesizer with a crystal oscillator and usually is converted in a limiter amplifier so that it can be further processed with digital frequency dividers. The stability of this reference signal determines the frequency stability of the entire arrangement. A number of cascaded divider stages divide the signal down to a lower value corresponding to the desired channel grid. A 10 kHz reference signal can be obtained, for example, from a 10.24 MHz crystal oscillator by means of ten 1: 2 divider stages connected in series.

The VCO signal is processed in a similar way to the reference signal, but in contrast to it is fed to a programmable frequency divider which thus has a variable division ratio. In a PLL of the down-mixing type, it is converted with the signal from another crystal oscillator, just like in a superhet receiver, and thus brought to a lower value. This has the advantage that the programmable divider does not have to process such high frequencies. Here we also have the option of fine-tuning by pulling the crystal frequency. This is why you can find the PLL synthesizer with down mixing inside of all devices for SSB, because at least one receiver fine tuning (clarifier) is required here.

The circuit shows a PLL synthesizer I built for test purposes with the specially designed IC NIS7261A. In conjunction with a suitable channel switch, all of the VCO frequencies required by a 40-channel CB radio with a first IF of 10,695 MHz can be generated. The channel switch used here came from an old CB radio from the USA. Using the containing 10.24 MHz crystal oscillator, at the same time the circuit supplies the oscillator signal required for mixing from the first IF to a second IF of 455 kHz. If a 37.85 MHz crystal is used instead of the 36.38 MHz crystal and the frequency is pulled down to 37.845 MHz with a series inductance, the circuit is suitable for controlling a 10m amateur radio device with a maximum channel frequency of exactly 29.700 MHz. Such a crystal can be found in many old 23-channel CB radios for AM.

In relation to a CB radio, the following relationships result with this PLL synthesizer: With a first IF of the receiver of 10.695 MHz, the VCO must oscillate to 37.66 MHz to receive CB channel 1 (= 26.965 MHz). The frequency fed to the adjustable divider is thus 1.28 MHz after down-mixing with the 36.38 MHz signal. The 10.24 MHz signal coming from the crystal oscillator provides a reference frequency of 10 kHz after division by 1024. So that a frequency of 10 kHz appears at the output of the programmable divider, the 1.28 MHz signal must be divided by 128. If the channel is now to be changed to channel 2 (= 26.975 MHz), the division ratio must be changed to 129. So that 10 kHz now appears at the output of the adjustable divider, the VCO is controlled so that its frequency changes to 37.67 MHz. For a VCO frequency of 38.1 MHz, which is required to receive channel 40 (= 27.405 MHz), the divider must be set to 172. Even with this division ratio, a 10kHz signal will appear at the output and the PLL can lock again. The fact that the frequency range with 40 channels is greater than 390 kHz is due to the special channel distribution in CB radio: The frequencies 26.995 MHz, 27.045 MHz, 27.095 MHz, 27.145 MHz and 27.195 MHz are internationally not intended for radio operation. Therefore the adjustable Dividers not with the division ratios of 131, 136, 141, 146 and 151 are allowed to work.

With the NIS7261A, binary information must be present on the control pins that exactly corresponds to the desired division ratio. The channel switch delivers the required logical high signals (H) from the 5-volt stabilizer, depending on the set channel. If there is no H signal, the level is logically low (L) via the so-called pull-down resistors (8x 10 kOhm). For a 10m radio device, everyone should now be able to calculate the corresponding ratios and required binary codes (dual system) for themselves. Incidentally, for transmitting, the VCO signal is mixed with that of a crystal oscillator that operates at a frequency of 10.695 MHz. With a different down-mixing frequency (e.g. 132 MHz with an IF of 10.7 MHz), the same circuit could also be used for a 2m radio, among other things. For the 12.5kHz grid, you would need a exemplar for 12.8 MHz instead of the 10.24 MHz crystal.

I tested such a PLL synthesizer with equally good success, but instead of the NIS7261A, it worked with standard ICs. The 10.24MHz oscillator was built with a 74LS00. This was followed by a dividing chain with 3 pieces 74LS93, whereby I left out the one input divider. Thus divided by two eleven times, the result is a reference frequency of 5 kHz. Two 74LS193 cascaded in reverse operation served as programmable dividers. The borrow signal activated the counter reading on the set lines, by means of which the dividing ratio could be programmed in exactly the same way as with the NIS7261A. The remaining divider from the 74LS93 divides the short 10kHz borrow pulses into 5 kHz, which resulted in a duty cycle of 1: 1. The 5 kHz phase comparison worked particularly well with a CD4046.

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